1. Field of the Invention
This invention relates generally to a method of manufacturing high density, high performance semiconductor devices having a hard mask layer formed on the metal stack to prevent DUV resist footings. Even more specifically, this invention relates to a method of manufacturing high density, high performance semiconductor devices using a single etcher to etch the hardmask and metal stack.
2. Discussion of the Related Art
The increased demand for high performance semiconductor devices has required the density of metallization lines to be increased. One of the major demands of end users of high performance semiconductor is an increase in raw processing speed. As more and more transistors have been packed onto the same semiconductor chip such as the microprocessor, the speed and functionality of the semiconductor chip have the potential to be increased significantly. With the increase in the number of transistors, more silicon area is required, however, the transistors need to be closer together to reduce the distance that electrons have to travel from one transistor to another via metal lines. However, as the metal lines have been placed closer together, there is an increased problem caused by reactance between the metal wires. One reactance problem is crosstalk caused by an inductive effect between the interconnections. Another reactance problem is related to an RC delay that is proportional to the operating frequency of the system. Because of the criticality of control of dimensions of structural components of semiconductor devices, any factor that increases or decreases any dimension can cause the performance of the semiconductor device to be less than design specification. The criticality of control is becoming even more critical and will become even more critical as dimensions decrease to the sub-0.25 .mu.m region.
The accelerated control of critical dimensions at the sub-0.5 .mu.m region for semiconductor manufacture has increased the interest of the semiconductor industry in anti-reflective coatings to reduce substrate reflectivity to a minimum and to prevent deep-UV resist footings. A paper by Wei W. Lee, Qizhi He, Guoqiang Xing, Abha Singh, Eden Zielinski, Ken Brennan, Girish Dixit, Kelly Taylor, Chien-Sung lian, J D Luttmer and Bob Havemann, entitled Inorganic ARC for 0.18 .mu.m and Sub-0.19 .mu.m Multilevel Metal Interconnects, discusses the use of Si.sub.x O.sub.y N.sub.z as an anti-reflective coating and also to serve as a hard mask layer. The paper reports the Si.sub.x O.sub.y N.sub.z reduces substrate reflectivity to a minimum and reduces deep-UV resist footing.
However, the use of a layer of a hardmask material such as Si.sub.x O.sub.y N.sub.z requires that the wafer be subjected to two separate etch processes, one to etch the hardmask material and another to etch the metal stack. Each of the separate etch processes requires a different etcher. The use of separate etchers and separate etch processes decreases throughput and adds cost to the process.
FIGS. 1A-1D show a method of manufacturing a semiconductor device without using an Si.sub.x O.sub.y N.sub.z layer. FIG. 1A shows a partially completed portion 100 of a semiconductor device. The partially completed portion 100 of the semiconductor device shows an oxide layer 102 that could be a layer of interlayer dielectric. A barrier layer 104 is formed on the oxide layer 102. The barrier layer could be a layer of Ti/TiN. A metallization layer 106 is formed on the barrier layer 104. The metallization layer 106 is formed from a conductive material such as aluminum. A layer 108 of an anti-reflective coating material is formed on the metallization layer 106. The layer 108 of anti-reflective material is formed from a material such as Ti/TiN.
FIG. 1B shows the partially completed prior art semiconductor device 100 as shown in FIG. 1A with a layer 110 of photoresist formed on the layer 108 of anti-reflective material.
FIG. 1C shows the partially completed prior art semiconductor device 100 as shown in FIG. 1B with the layer 110 of photoresist patterned and etched down to the layer 108 of anti-reflective material. As indicated at 112, structures known as resist footings are formed at the interface between the layer 110 of photoresist and the layer 108 of anti-reflective material. It is theorized that the formation of the resist footings 112 is caused by the nitrogen in the layer 108 of anti-reflective material reacting with the layer 110 of photoresist.
FIG. 1D shows the partially completed prior art semiconductor device 100 as shown in FIG. 1C after a series of etch processes to etch the layer 108, the metal layer 106, and the barrier layer 104 down to the layer 102 of oxide. When the etch processes are completed, it is noted that the resist footings 112 has prevented vertical profiles from being formed in the etched portions. The dimension 114 indicates the desired dimension and the dimension 116 shows the resulting dimension and indicates that the resist footing results in a relatively large reduction from the desired dimension 114. The criticality of the decrease in dimension can be appreciated from the fact that the designed metal line width for a typical process is approximately 0.35 .mu.m and the spaces between the metal lines are designed to be less than 0.30 .mu.m. Other processes have similar dimensions and future processes will have smaller dimensions.
FIG. 3 is a flow diagram showing a prior art method of manufacturing wafers. The manufacturing process starts at 300. The manufacturing process includes a series of processes 302 that form active devices in a substrate in the wafer. After the active devices are formed on and in the substrate, an initial layer of interlayer dielectric is formed on the surface of the substrate and a metal layer (stack), indicated at 304, including a hardmask layer is formed on the layer of interlayer dielectric. A layer of photoresist is formed on the hardmask layer, patterned and developed to expose portions of the hardmask layer, indicated at 306, and the wafer is placed in a first etcher to etch the hard mask layer, indicated at 308. After the hardmask layer is etched, the wafer is placed in a second etcher, indicated at 310, to etch the metal layer. After the process in the second etcher is finished, it is determined at 312 if the metal layer just etched is the last metal layer. If it is not, the wafer is further processed at 314 and the next metal layer is formed at 304. This process is continued until it is determined at 312 that the metal layer just completed is the last layer. When the last layer is finished, the wafer is finished 316. The requirement to use two etchers decreases throughput and increases the cost of the process.
Therefore, what is needed is a method of manufacturing a semiconductor device that does not form resist footings that provide non-vertical profiles in etched structures and in addition provides a method that utilizes one etcher to etch both the hardmask layer and the metal layer.